1. Field of the Invention
The present invention relates to the field of integrated circuits. More specifically, it relates to a method for programming antifuses in dynamic random access memory (DRAM) using a signal from a global column decoder and a programming line with which the antifuse is paired.
2. Description of the Related Art
Typical DRAM circuits include arrays of memory cells arranged in rows and columns. Each of the rows and columns are driven by a respective row decoder and column decoder. Typically, these memory circuits include several redundant rows and columns that are used as substitutes for defective locations in the memory array. For example, rather than having 1024 columns (i.e., 210 columns), a typical array might have 1028 columns, along with 1028 column decoders.
As is depicted in FIG. 1, normal practice is for the column decoders CD1, CD2, CD3, CD4 . . . CDN to receive memory cell addresses (e.g., during a normal read or write operation) coming from external sites (e.g., external pads). Before the addresses reach the column decoders, they may be passed through one or all of a series of buffers, and/or redundancy decoders. The addresses then reach the column decoders where they are cascaded through the column decoders until the address data reaches the one particular column decoder that matches the incoming address. Each of the column decoders is also coupled to a corresponding Y-gate driver, or inverter I1, I2, I3, I4 . . . IN. During a normal read or write operation, only one of the column decoders (i.e., only one of 1028) is set high at a time. That is, when the address is fully decoded as corresponding to a particular column decoder, that column decoder is set logic high (e.g., 1) while all others remain logic low (e.g., 0).
Typically, the logic high signal of the column decoder is sent across the entire memory array 10 (e.g., which may consist of as many as 16 sub-array blocks tiled side by side) where it is coupled to sense amplifiers (not shown) between every block.
When a defective memory array location has been identified, a repair is effected. Rather than treating the entire array as defective, one of the redundant rows or columns are substituted for a defective row or column. This substitution is performed by assigning the address of the defective row or column to the redundant row or column and decoding the address with a redundant column decoder such that, when an address signal corresponding to a defective row or column is received by one of said column decoders CD1, CD2, CD3, CD4 . . . CDN, and the redundant column decoder the redundant row or column is addressed instead: This makes the substitution of the redundant row or column substantially transparent to a system employing the memory circuit.
An example of fuse blowing is found in the programming of sense lines. Fusebank address detection circuits employ a bank of sense lines where each sense line corresponds to a bit of an address. The sense lines are programmed by blowing fuses in the sense lines in patterns corresponding to the address of the defective row or column.
Traditionally, the fuses have been blown by having a laser cut the fuse conductors to remove the conductive paths through the fuses. One problem with such an approach is that the laser cutting of the fuses is time consuming, difficult and imprecise. Therefore, the cost and reliability of memory devices employing laser fuse bank circuits can be less than satisfactory.
More recently, memory devices have been employing antifuse banks in place of conventional fuses. Antifuses are capacitive-type structures that, in their unblown states, form open circuits. Antifuses may be blown by applying a high voltage across the antifuse. The high voltage causes the capacitive-type structure to break down, forming a conductive path through the antifuse. Therefore, blown antifuses conduct and unblown antifuses do not conduct.
While redundant repair is one goal associated with the blowing of antifuses, as is known in the art, antifuses may be blown e.g., to change the state of another signal associated with a bad column, or to lessen defect currents, etc.
Typically, the current practice is to locate antifuse banks at a periphery of a memory array block where separate antifuse electrical decode circuitry is require in order to determine which particular antifuse is to be programmed. The separate antifuse decoder circuitry comprises a second set of address decoding circuitry (i.e., in addition to the already existing column decoders) for determining which antifuse is to be programmed and eventually blown.
The separate antifuse decoder circuitry, located adjacent to the antifuse bank and also at a periphery of the memory array, receives address data from the address lines that are coupled to the global column decoders. That is, the separate antifuse address decoder circuitry receives the same address information as received by the global column decoder which has been selected (e.g., during normal read or write operations) only to redundantly perform the address decode operation again so as to determine which antifuse is to be programmed.
For example, assuming a typical memory array capacity of 64Mb; such an array comprises 512 global column decode lines, which correspond to 9 address bits that require decoding (i.e., 29=512). Therefore, when the antifuse decoding is performed within the antifuse bank itself, by a local address decoder, a total of 18 address bit lines (i.e., 9 ADDRESS lines and 9 {overscore (ADDRESS)} lines) must be routed from an address decoding section of the DRAM to a periphery of the DRAM (where such antifuse banks are ideally located) where the addresses are locally decoded within the antifuse bank. After the address lines are locally decoded, the blowing of a particular antifuse (as determined by the address decoder) is enabled. This extraneous routing of the address lines severely complicates integrated circuit (IC) design, thereby resulting in larger die-size and increased manufacturing costs.
Therefore, rather than taking advantage of existing IC designs and the logic high signal (e.g., 1) that is already being produced by the column decoders, the programming of antifuses associated with, e.g., column repair, column preconditioning, etc., are typically performed as described above. Thus there exists a need for a system and method for programming antifuses, thereby selecting the antifuses to be blown, without requiring additional circuitry in the form of a local address decoder at the antifuse bank, and without requiring the extraneous routing of address lines to a periphery of a DRAM.
The present invention overcomes the problems associated with the prior art and provides a system and method for programming antifuses without requiring additional address decoder circuitry at the antifuse bank and without requiring the routing of address lines to a periphery of a DRAM.
In accordance with a preferred embodiment of the present invention, a separate antifuse is provided for each global column decoder. Therefore, setting only one column decoder to logic high (e.g., for each read or write cycle, or for an address entered by an operator through the pad during preconditioning) not only activates the corresponding column of the memory cell array, but also provides the enable signal to program a corresponding antifuse sitting on that same global select program line. That is, when a column decoder is set logic high, the particular antifuse sitting on that same line receives the same logic high signal, thereby indicating that that particular antifuse has been selected to be blown. Accordingly, a xe2x80x9cpop voltagexe2x80x9d (i.e., the voltage required to blow the antifuse) is routed to that particular antifuse from a source that is external to the antifuse bank.
The present invention provides a method and system for programming antifuses, e.g., as used in connection with DRAMs, without requiring additional address decoder circuitry at the antifuse bank. The invention utilizes already existing DRAM address decoder circuitry to effectively program a particular antifuse.